Clock synchronization in a communications network is the means by which a clock signal is generated or derived and distributed through the network and its individual nodes for the purpose of ensuring synchronized network operation. Two main performance degradation issues come into play when clocks at a transmitter and a receiver are not synchronized. First, if the physical interfaces along a connection are not synchronized (i.e., not driven by a clocking signal of identical frequency), data can be lost due to buffer overflow or underflow, resulting in periodic line errors. Second, imperfections in clock synchronization can lead to observable defects on an end service such as bit errors due to alignment jitter or frame slips.
In packet switched networks such as IP/Ethernet where essentially an asynchronous transmission service is provided, the synchronization needs of real-time applications are difficult to meet. Many techniques have been proposed to effectuate clock synchronization in a packet switched network. In one approach, a receiver may derive an estimate of the transmitter clock from the received data stream. For example, a transmitter may send an explicit time indication or timestamp (e.g., in a packet with or without user data) to a receiver so that it can synchronize its local clock to that of the transmitter. Since no common network clock is used, the receiver relies on locking a recovered clock to the arrival of the timestamp patterns. This is commonly done using a phase-locked loop (PLL) that slaves the receiver clock to a transmitter clock. The PLL is able to process transmitted clock samples encoded within the data stream, or process data arrival patterns to generate a timing signal for the receiver. The purpose of the PLL is to estimate and compensate for the frequency drift occurring between the oscillators of the transmitter clock and the receiver clock. Unfortunately, the presence of transmission jitter affects the performance of the clock estimation/compensation process, making the transmitter clock appear faster or slower than it actually is, and ultimately, causing the propagation of some residual jitter to the receiver clock signal. The presence of even a modest amount of jitter makes the clock recovery problem difficult. The design of the PLL must ensure that clock impairments are within acceptable limits for the intended applications.
One significant problem with existing PLL clock recovery circuits arises from the poor performance of their loop filters. When a loop filter fails to effectively suppress the high frequency component of the detected clock error, the PLL will not acquire or maintain a true lock to the transmitter frequency. This problem may be best understood with reference to FIGS. 1 through 3.
In FIG. 1, there is shown a loop filter 10 comprising a double exponentially weighted moving average (EWMA) filter. The double EWMA filter comprises a first EWMA filter 11 cascaded with a second EWMA filter 12. The first EWMA filter 11 comprises a first multiplying element 100, a summing junction 102, a delay element 104, a second multiplying element 106, a differencing element 108, a constant element 110 and a gain element 112. Similarly, the second EWMA filter 12 comprises a first multiplying element 114, a summing junction 116, a delay element 118, a second multiplying element 120, a differencing element 122, a constant element 124 and a gain element 126.
In practice, a detected clock error signal e(n) is fed to the input of EWMA filter 11, a first output signal s(n) is generated at the output of EWMA filter 11, and a second output signal u(n) is generated at the output of EWMA filter 12, where integer n indicates the arrival time of the nth timestamp. These signals have the following relationship:s(n)=α1*e(n)+(1−α1)*s(n−1)u(n)=α2*s(n)+(1−α2)*u(n−1)where α1 and α2 can be tuned to achieve an optimized loop filter response. Theoretically, if the high frequency component of e(n) can be removed by loop filter 10, the frequency of timestamp generation can be estimated to an arbitrary degree of accuracy. However, in reality, even with both α1 and α2 optimized, a continual build-up of phase error can still be observed. As a result, the PLL will never truly lock to the transmitter clock frequency. FIG. 2 shows the build-up of phase error in a PLL incorporating loop filter 10. FIG. 3 shows the frequency response of such a PLL where waveform 302 is the transmitter frequency and waveform 304 is the PLL output frequency. It can be seen that waveform 304 fails to trace the transmitter frequency.
In view of the foregoing, it would be desirable to provide a technique for clock synchronization which overcomes the above-described inadequacies and shortcomings.